Project BriefOpen Competition 3 - Electronics and Photonics (September 2002)Nano-Imprint Lithography Infrastructure for Low Cost Replication at the 65 nm Node and BeyondDesign and demonstrate technology for step and flash imprint lithography (S-FIL), a novel method of transferring integrated circuit patterns to the surface of a semiconductor wafer by molding of three-dimensional features potentially as small as 20 nanometers or less. Sponsor: Molecular Imprints, Inc.1870C W. Braker LaneSuite 100 Austin, TX 78758
Photolithography, long used to transfer integrated circuit patterns to the surface of a silicon wafer, is becoming so costly that future growth of the $150 billion semiconductor industry is in jeopardy. Furthermore, the lithography advances required to make features smaller than 65 nanometers (nm), as required by industry roadmaps, are daunting. An alternative lithography process is proposed by a joint venture led by Molecular Imprints which plans a three-year project to design and demonstrate technology for high-resolution imprinting of device patterns. Step and flash imprint lithography (S-FIL), invented at the University of Texas (UT) at Austin, involves the use of topographical templates to mold three-dimensional patterns potentially as small as 20 nm or less. Unlike traditional optical lithography, S-FIL does not require expensive optics, advanced illumination sources, or specialized resists; unlike traditional thermal imprinting, the process works at room temperature and low pressure. The template is made of fused silica; an ultraviolet light-curable photoresist solution is dispensed in nano-volume droplets between the template and a semiconductor wafer. After illumination and curing of the photoresist, the template is separated from the wafer, a residual layer is removed, and features are etched. The Molecular Imprints project seeks to mitigate the technology risks associated with the implementation of S-FIL into microelectronics fabrication at the 65 nanometer node and beyond. The project team will design high-resolution, 1X prototype templates and attempt to pattern dense vias/contacts (a critical lithography level) at the 65 nm node, achieving appropriate overlay alignment, control of critical dimensions, and adequate throughput and yield. In addition, they will identify barriers to extending the technology to the 45 nm node and beyond. Technical challenges will include achieving a low defect imprint process suitable for high volume CMOS fabrication and etching features with high aspect ratios. Participants include Motorola Labs (Tempe, Ariz.), Photronics, Inc. (Brookfield, Conn.), KLA-Tencor Corp. (Milpitas, Calif.), and UT. Because of the very high risk involved, the research would not proceed without ATP funding, which was critical in bringing together the multidisciplinary research team. If successful, the project could save $540 million annually in lithography costs worldwide, including $216 million in the United States, and could reestablish the U.S. lithography equipment industry. S-FIL also has application in life science, nanotechnology, and biotechnology.
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